Buffer circuits for use with semiconductor memory devices

ABSTRACT

In a buffer circuit for producing two output signals of the opposite phases in response to an input signal comprising a pre-circuit producing two pre-output signals in accordance with the input signal and a reference voltage signal; and a main circuit including a latch circuit latching the pre-output signals, and a flip-flop circuit connected to receive the pre-output signals latched by the latch circuit for producing the output signals of the buffer circuit, there is provided a transfer gate circuit enabled by the pre-output signals and disabled by the output signals of the buffer circuit. According to this invention, different from the prior art circuit, it is not necessary to use any clock signal having a high level at the time of operation of the buffer circuit and to have strict time spacing, whereby the clock signal generator can be simplified and the buffer circuit can be miniaturized and its operating speed can be increased.

BACKGROUND OF THE INVENTION

This invention relates to a buffer circuit.

A buffer circuit which produces two output signals having oppositephases (hereinafter termed opposite output signals) in response to asingle input signal is constructed to compare the input signal with apredetermined reference voltage signal for obtaining two opposite outputsignals and is important as a buffer element between an input circuitand an internal circuit in various electronic circuits. As the capacityof memory devices increases and as their operating speed increases, soan address buffer circuit for use with semiconductor memory devicesbecomes important. For this reason, in the following description, anaddress buffer circuit utilized in a semiconductor memory device istaken as a typical example.

An address buffer circuit is used in a semiconductor memory device forsending an address selection designation signal to a decoding circuit inaccordance with an address input signal, and it is required in such anaddress buffer circuit that it accurately determine a designated addressand operate at a high sensitivity and high speed, that its powerconsumption be small, that it includes a signal generating circuit, andthat it can be designed readily and reduced in size for miniaturizationof the chip.

Various circuits have been proposed which meet these requirements. FIG.1 shows one example of the most advanced prior art circuit.

The circuit shown in FIG. 1 comprises a pre-circuit 11 essentiallyconstituted by a flip-flop circuit which is made up of enhancement typefield effect transistors (E-FET) Q₃₁ and Q₃₂ and which compares a singleinput signal A_(I) with a predetermined reference voltage signal V_(REF)to produce two opposite pre-output signals A'_(o) and A'_(o), and a maincircuit 12 essentially constituted by another flip-flop circuit made upof E-FETs Q₄₁ and Q₄₂ acting as a transfer gate which transfers thepre-output signals A'_(o) and A'_(o) according to a clock signal P₁₁,and E-FETs Q₄₇ and Q₄₈ which produce two opposite output signals A_(o)and A_(o) when supplied with the pre-output signals A'_(o) and A'_(o).One of the characteristic features of this circuit lies in thatdepletion type field effect transistors (D-FET) Q₃₃ Q₃₄, Q₃₅ and Q₃₆ areused in the pre-circuit. The operation of this circuit will be outlinedas follows.

The operation of the pre-circuit will first be described. According to aclock signal φ₁₁, the input signal A_(I) giving an address input and thereference voltage signal V_(REF) are applied to nodes N₁₃ and N₁₄ viaE-FETs (in the following merely designated as FET except D-FET) Q₃₇ andQ₃₈. While latching the applied signals by the clock signal φ₁₁, a clocksignal φ₁₂ rises to raise the potential of these nodes N₁₃ and N₁₄ bythe action of bootstrap capacitances C₁₁ and C₁₂. As a consequence, theconductivity of each of D-FETS Q₃₅ and Q₃₆ is caused to vary by theapplied input signal A_(I) and reference voltage signal V_(REF). Such achange is detected by the flip-flop circuit constituted by FETs Q₃₁ andQ₃₂ by making a clock signal φ₁₁ low level which appears at nodes N₁₁and N₁₂ and is then sent out to the main circuit 12 as the pre-outputsignals A'_(o) and A'_(o) via FETs Q₃₉ and Q₄₀. If the clock signal φ₁₁is still at a low level even after detection by the flip-flop circuit,the D-FETs Q₃₃ and Q₃₄ on the load side would be turned ON, therebyincreasing power consumption. Accordingly, a one shot reverse phasesignal as shown in FIG. 2 is used as the clock signal φ₁₁. Since theclock signal φ₁₁ is a one shot reverse phase signal, as the clock signalφ₁₁ rises again, the nodes N₁₁ and N₁₂ will be precharged through D-FETsQ₃₃ and Q₃₄ again, whereby their address determination information atthe nodes N₁₁ and N₁₂ would be lost, and levels at the nodes N₁₅ and N₁₆would be also lost. Thus, the FETs Q₄₁ and Q₄₂ are provided for thepurpose of preventing such loss by separating the nodes N₁₅ and N₁₆ fromthe nodes N₁₁ and N₁₂ which are kept at high potential levels. The FETsQ₄₁ and Q₄₂ act as a transfer gate so that pre-output signals A'_(o) andA'_(o) are applied to nodes N₁₅ and N₁₆ in the main circuit 12 inaccordance with a clock signal P₁₁ and then detected by the flip-flopcircuit comprising FETs Q₄₇ and Q₄₈. The detected signals are outputtedas output signals A_(o) and A_(o) from output terminals 15 and 16. Thecircuit constituted by FETs Q₄₃, Q₄₅ and Q₄₄ and Q₄₆ is an output levelensuring circuit which produces an output having the same level as thatof a clock signal φ₁₃ by bringing the potential levels of nodes N₁₇ andN₁₈ up to the levels above the level of the clock signal φ₁₃ byself-boost effect caused by gate-source capacitances of FETs Q₄₅ andQ.sub. 46. The FETs Q₄₉ and Q₅₀ are provided for the purpose ofpreventing a low level floating in which a low level one of thepre-output signals A'_(o) and A'_(o) is maintained directly by a highlevel one of the output signals A_(o) and A'_(o) to turn ON onereceiving such high level signal of FETs Q₄₉ and Q₅₀.

As described above, although this prior art circuit is advantageous inthat its main circuit 12 is simple and compact in construction, it stillinvolves the following problems. For example, the output information ofthe pre-circuit 11 which is transmitted to the nodes N₁₅ and N₁₆ isdirectly controlled by the output signals A_(o) and A_(o) through FETsQ₄₉ and Q₅₀. When the output signals A_(o) and A_(o) float, the outputsat the nodes N₁₅ and N₁₆ are lost. Consequently, as shown in FIG. 2,this circuit is inherently sensitive to mutual differences in timingbetween clock signals φ₁₁, P₁₁ and φ₁₃. For example, should the clocksignal P₁₁ becomes a low level before the clock signal φ₁₁ becomessufficiently low level, the main circuit would be disconnected from thepre-circuit before the address information is determined by the maincircuit. This requires the clock signal generator to ensure correcttiming. Such ensurance can be attained by increasing the time spacing(i.e. lowering frequency) but such expedient prevents high speedoperations. Furthermore, as the clock signal φ₁₃ is required not only todirectly maintain the output signal level, but also to drive a decodercircuit constituting the load of the address buffer circuit, it becomesnecessary to provide a high power clock signal generating circuit havinga high level of V_(DD). Such a circuit is complicated and uses largetransistors, thereby preventing miniaturization of the chip.

Other prior art circuits also, require a clock signal that rises to theV_(DD) source voltage level at the time of detection. In addition, thereis the problem of time spacing described above. Accordingly, therequirement for clock signal generating circuit is severe, which makesit complex and difficult to design the circuit and preventsminiaturization of the circuit and high speed operation thereof.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide an improvedbuffer circuit in which the requirements for the voltage and timespacing of clock signals necessary for proper operation are not sosevere as in the prior art buffer circuit so that the clock signalgenerating circuit can be designed readily to have a compact size andcan operate at a high speed.

According to this invention, there is provided a buffer circuit whichproduces two output signals of opposite phases in response to an inputsignal, characterized in that there are provided a pre-circuit producingtwo pre-output signals in accordance with the input signal and areference voltage signal; and a main circuit including a transfer gatecircuit enabled by the pre-output signals and disabled by the outputsignals of the buffer circuit, a latch circuit latching the pre-outputsignals, and a flip-flop circuit connected to receive the pre-outputsignals latched by the latch circuit for producing the output signals ofthe buffer circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 shows a connection diagram of a prior art buffer circuit;

FIG. 2 shows waveforms of clock signal voltages utilized in the circuitshown in FIG. 1;

FIG. 3 is a connection diagram showing one embodiment of the buffercircuit according to this invention;

FIG. 4 shows waveforms of node potentials and clock signal voltages ofthe circuit shown in FIG. 3; and

FIG. 5 shows waveforms of the clock signal voltages utilized in thecircuit shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the buffer circuit of this inventionillustrated in FIG. 3 is constituted by a pre-circuit 1 which producestwo opposite pre-signals A'_(o) and A'_(o) in response to an addressdesignation input signal A_(I) impressed upon an input terminal 3 and areference voltage signal V_(REF) impressed upon a reference voltageterminal 4, and a main circuit 2 supplied with the pre-output signalsA'_(o) and A'_(o) for performing an address judgement to produce twooutput signals A_(o) and A_(o) of opposite phases and havingpredetermined levels.

The pre-circuit 11 has the same construction as that 11 shown in FIG. 1.More particularly, the pre-circuit 1 is constituted by FETs Q₁ and Q₂which form a flip-flop circuit cross-connected at nodes N₁ and N₂, withtheir source electrode common junction driven by a clock signal φ₁,D-FETs Q₃ and Q₄ respectively connected between the FETs Q₁ and Q₂ and aV_(DD) source terminal with their gate electrodes commonlyinterconnected to be driven by the clock signal φ₁, D-FETs Q₅ and Q₆respectively connected between the nodes N₁ and N₂ and the V_(DD) sourceterminal, FETs Q₇ and Q₈ respectively having drain electrodes forforming nodes N₃ and N₄ together with the gate electrodes of the D-FETsQ₅ and Q₆, the gate electrodes of FETs Q₇ and Q₈ being driven by theclock signal φ₁ and the source electrodes of the FETs Q₇ and Q₈ beingconnected to the input signal terminal 3 and the reference voltagesignal terminal 4, respectively, bootstrap capacitors C₁ and C₂respectively connected to the nodes N₃ and N₄ to be driven by a clocksignal φ₂, and FETs Q₉ and Q₁₀ with their drain electrodes connected tothe nodes N₁ and N₂, the gate electrodes commonly connected to the gateelectrodes of FETs Q₁ and Q.sub. 2 and source electrode acting as outputnodes N₅ and N₆ of the pre-output signals A'_(o) and A'_(o).

The main circuit 2 is constituted by FETs Q₁₁ and Q₁₂ cross-connected atnodes N₇ and N₈ to form a flip-flop circuit, the nodes N₇ and N₈ formingoutput terminals 5 and 6 of output signals A_(o) and A_(o) respectively;FETs Q₁₃ and Q₁₄ with their source electrodes connected to nodes N₇ andN₈ and gate electrodes connected to nodes N₈ and N₇ respectively; FETsQ₁₅ and Q₁₆ with their source electrodes connected to the drainelectrodes of FETs Q₁₃ and Q₁₄ respectively, drain electrodes connectedto source electrodes of FETs Q₉ and Q₁₀ for forming the nodes N₅ and N₆acting as output and input terminals of the pre-output signals A'_(o)and A'_(o), and the gate electrodes connected to the gate electrodes ofFETs Q₁₄ and Q₁₃ respectively; FETs Q₁₇ and Q₁₈ with their sourceelectrodes connected to the nodes N₇ and N₈ respectively, drainelectrodes connected to the V_(DD) source terminal, and gate electrodesconnected to drain electrodes of FETs Q₁₃ and Q₁₄ to form nodes N₉ andN₁₀ ; bootstrap capacitors C₃ and C₄ respectively connected to the nodesN₉ and N₁₀ and driven by a clock signal φ₂ ; and FETs Q₁₉ and Q₂₀ withtheir source electrodes connected to the nodes N₇ and N₈, drainelectrodes connected to the V_(DD) source terminal, and gate electrodesconnected to be driven by a clock signal P₁. The flip-flop circuitcomprised of the FETs Q₁₁ and Q₁₂ is connected to receive a clock pulseφ3.

The operation of the embodiment shown in FIG. 3 will now be describedwith reference to the node potentials and clock signal voltages shown inFIG. 4. For the sake of description, it is assumed that the input signalA_(I) is at a high level.

Firstly, the level of the clock signal P₁ is raised to the level ofV_(DD), if necessary, higher than V_(DD) to precharge the output nodesN₇ and N₈ to a sufficiently high level and the levels of the clocksignals φ₁ and φ₂ are raised to a level slightly lower than that of theV_(DD). The input signal A_(I) at the high level and the referencevoltage signal V_(REF) are applied to respective input terminals 3 and4. Accordingly, both FETs Q₇ and Q₈ are turned ON to apply the inputsignal A_(I) to the node N₃ and the reference voltage signal V_(REF) tothe node N₄. Also the nodes N₁ and N₂ are precharged to the level ofsource V_(DD) by the D-FETs Q₃ and Q₄, and the flip-flop circuitconstituted by FETs Q₁ and Q₂ is in an inoperative state. On the otherhand, in the main circuit, FETs Q₁₉ and Q₂₀ are turned ON to prechargethe nodes N₇ and N₈ to the level of the source voltage V_(DD), with theresult that FETs Q₁₃ and Q₁₄ are turned ON to precharge the nodes N₉ andN₁₀ to the level of the source voltage V_(DD). Thus, FETs Q₁₅ and Q₁₆acting as a transfer gate are turned OFF since nodes N₅ and N₆ arecharged to a high potential through FETs Q₉ and Q₁₀, whereby thepre-circuit is disconnected from the main circuit.

Then, the level of the clock signal P₁ is lowered (to source potentialV_(SS) or ground potential), the clock signal φ₂ is raised to a levelslightly lower than that of the source voltage V_(DD) and the clocksignal φ₁ is lowered to a low level. Accordingly, the nodes N₃ and N₄are raised to high potentials by way of the bootstrap capacitors C₁ andC₂ to make different the capability of D-FETs Q₅ and Q₆, which changesthe potentials of the nodes N₁ and N₂. The difference is judged by theflip-flop circuit constituted by FETs Q₁ and Q₂ and the result ofjudgement appears at the output nodes N₅ and N₆ of the pre-circuit viaFETs Q₉ and Q₁₀ as the pre-output signals A'_(o) and A'_(o). On theother hand, in the main circuit, the potentials of nodes N₉ and N₁₀ areraised to levels higher than the level of the source voltage V_(DD) bythe clock signal φ₂ through the medium of the bootstrap capacitors C₃and C₄.

Under this state, when the pre-output signals A'_(o) and A_(o) from thepre-circuit appear at nodes N₅ and N₆, the FET Q₁₆ on the lower levelside (since at this time the input signal A_(I) is at the high level,signal A'_(o) is at the low level) acting as a transfer gate is turnedON to lower the potential of the node N₁₀ to a low level. As aconsequence, the capability of FETs Q₁₇ and Q₁₈ is greatly variedwhereby the potentials of nodes N₇ and N₈ vary correspondingly. In otherwords, the output signals A'_(o) and A'_(o) of the pre-circuit arelatched by FETs Q₁₇ and Q₁₈. The potential level difference at nodes N₇and N₈ is amplified and judged by the flip-flop circuit constituted byFETs Q₁₁ and Q₁₂ by lowering the level of the clock signal φ3 from highto low level to produce output signals A_(o) and A_(o) (in this case,A_(o) is the low level signal) at the output terminals 5 and 6,respectively, and these output signals are positively fedback to thenodes N₉ and N₁₀ respectively through FETs Q₁₃ and Q₁₄. As the outputnode N₈ becomes the low level, the FET Q₁₆ automatically turns OFF sincethe potential of node N₁₀ is lowered as a result of turning ON of FETQ₁₄ due to the high potential of node N₇, whereby the pre-circuit andthe main circuit are disconnected again. Consequently, even when thepotential of the clock signal φ₁ is increased for the purpose ofpreventing increase in the power consumption caused by turning ON D-FETsQ₃ and Q₄ after the judgement effected in the pre-circuit 1, the maincircuit 2 will not be influenced. FIG. 5 shows only the clock signalsamong various waveforms shown in FIG. 4 and the clock signals aredepicted to correspond to those shown in FIG. 2.

As described above, the circuit of this embodiment requires 4 clocksignals P₁, φ₁, φ₂ and φ₃ as shown in FIG. 5 just in the same manner asin the prior art. However, signal P₁ is used to precharge the outputnodes N₇ and N₈ to a suitable potential, and may simply be of the samelevel as that of the source voltage V_(DD) or more, if necessary.Accordingly, different from the clock signal P₁₁ necessary for directlydriving the transfer gate as in the prior art, the clock signal P₁ isnot required to have a high level like V_(DD) and a strictly definedtime spacing (see FIG. 2). The clock signal φ₁ is a one shot oppositephase signal like the prior art for the purpose of decreasing the powerconsumption caused by the turning ON of the D-FETs Q₃ and Q₄ in thepre-circuit after the address judgement. The clock signal φ₂ is used todrive the bootstrap capacitors C₁, C₂, C₃ and C₄ for raising thepotentials of nodes N₃, N₄, N₉ and N₁₀. According to this invention,although the number of the nodes whose potentials are to be increased by2 as compared to the prior art circuit, the high level is lower thanthat of the source voltage V_(DD), thus causing no problem. The clocksignal φ₃ is used to activate the flip-flop circuit comprising FETs Q₁₁and Q₁₂ for judging the address level and its level is changed from alevel slightly lower than that of V_(DD) to a much lower level, withoutrequiring any special change. For this reason, in the circuit shown inFIG. 3, it is not necessary to use the strictly defined signal φ₁₃(shown in FIG. 2) adapted to directly drive a load, which signal isrequired to have strict time spacings with respect to other signals asin the prior art circuit, and further required to have a higher levelthan V_(DD) sufficient to self-boot the nodes N₁₇ and N₁₈ (see FIG. 1)to above V_(DD).

Thus, according to the circuit shown in FIG. 3, among various clocksignals, the one necessary for the activation during judgement is notrequired to have strict voltage and time spacing so that it is notnecessary to enlarge the time spacing, to use a complicated circuit orlarge capacity transistors. Thus, the clock signal generating circuitcan be readily designed, thus ensuring miniaturization and high speedoperation of the memory circuit.

Although, in the foregoing embodiment, the buffer circuit has beendescribed by way of an address buffer circuit for a semiconductor memorydevice, the invention may also be applied to any circuit of a similartype.

As described above, the buffer circuit of this invention is constitutedby a pre-circuit producing two pre-output signals having opposite phasesin response to an input signal; and a main circuit comprising a transfergate circuit enabled by the pre-output signal and disabled by the outputof the buffer circuit, a latch circuit for latching the pre-outputsignals, and a flip-flop circuit supplied with the pre-output signalslatched by the latch circuit. As a consequence, different from the priorart circuit, it is not necessary to use any clock signal required tohave high levels equal to the level of the source voltage V_(DD) andstrict time spacing during the activation (judging operation) of thecircuit, thereby simplifying the design of the clock signal generatingcircuit, miniaturizing the entire circuit and increasing the operatingspeed.

What is claimed is:
 1. In a buffer circuit for producing two outputsignals of opposite phases in response to an input signal comprising apre-circuit producing two pre-output signals in accordance with saidinput signal and a reference voltage signal; and a main circuitincluding output nodes, a sample and hold circuit for sampling andholding said pre-output signals, and a flip-flop circuit connected toreceive said pre-output signals for producing the output signals of thebuffer a circuit, the improvement wherein said main circuit comprises atransfer gate circuit enabled by said pre-output signals and disabled bysaid output signals of the buffer circuit.
 2. A buffer circuit accordingto claim 1 wherein said main circuit comprises a control circuitresponsive to said pre-output signal to disable, in the presence of aclock signal for pre-charging the output nodes of the main circuit, thetransfer gate circuit when said input signal and reference voltage areof the same level and enable, in the absence of the pre-charging clocksignal, the transfer gate circuit when said input signal and referencevoltage are of different levels.
 3. A buffer circuit according to claim1 wherein said transfer circuit comprises a first pair of field effecttransistors with their source electrodes connected to one output nodeand the other output node of the main circuit, respectively, and gateelectrodes connected respectively to said other node and said one node;a second pair of field effect transistors with their source electrodesconnected to the drain electrodes of the first pair of field effecttransistors with their source electrodes connected to the drainelectrodes of the first pair of field effect transistors, drainelectrodes connected to receive said pre-output signals, and gateelectrodes connected to the gate electrodes of the first pair of fieldeffect transistors; and bootstrap capacitors respectively connected atone end to the node between the drain electrode of the first pair offield effect transistors and the source electrode of the second pair offield effect transistors and to a terminal for receiving a bootstrapsignal at a second end.
 4. A buffer circuit comprising first and secondinput nodes, a flip-flop circuit having first and second input/outputnodes, means for operatively charging said first and second input/outputnodes with a predetermined potential, a first series circuit of thedrain-source current paths of first and second field effect transistors,a second series circuit of the drain-source current paths of third andfourth field effect transistors, said first series circuit beingconnected between said first input node and said first input/outputnode, said second series circuit being connected between said secondinput node and said second input/output node, means for connecting thegates of said first and fourth transistors to said first input/outputnode, and means for connecting the gates of said second and thirdtransistors to said second input/output node.
 5. A buffer circuitaccording to claim 4, further comprising a fifth field effect transistorhaving its drain-source current path coupled between a power voltageterminal and said first input/output node and having a gate coupled tothe intermediate junction of said first series circuit, and a sixthfield effect transistor having its drain-source current path coupledbetween said power voltage terminal and said second input/output nodeand having a gate coupled to the intermediate junction of said secondseries circuit.
 6. A buffer circuit according to claim 4, furthercomprising a pre-circuit for generating true and complementary signalsas a result of comparing an input signal with a reference voltage, andmeans for applying said true and complimentary signals to said first andsecond input nodes.
 7. A buffer circuit according to claim 5, furthercomprising a first capacitor coupled to said intermediate junction ofsaid first series circuit at one end, a second capacitor coupled to saidintermediate junction of said second series circuit at one end, andmeans for applying a clock signal to the other ends of said first andsecond capacitors.